Please note that the updated list is maintained at our IML Web site.
An old sample of publications as of Spring 2007 is below.
Books

K. Radecka and Z. Zilic, "Verification by Error Modeling: Using Testing Techniques for Hardware Verification" , Kluwer Academic Publishers, 2003.
Journal Papers
 Z. Zilic and K. Radecka, "Scaling and Better Approximating Quantum Fourier Transform by Higher Radices", IEEE Transactions on Computers (Special Issue on NanoSystems and Computing), Vol. 56, No. 2, pp. 202207, February 2007.

K. Radecka and Z. Zilic, "Arithmetic Transforms for Compositions of Sequential and Imprecise Datapaths", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pp. 13821391, July 2006.

A. Chattopadhyay and Z. Zilic, "GALDS: A Complete Framework for Designing Multiclock ASICs and SoCs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 6, pp. 641654, Jun. 2005.

K. Radecka and Z. Zilic, "Design Verification by Test Vectors and Arithmetic Transform Universal Test Sets", IEEE Transactions on Computers , Vol. 53, No. 5, pp. 628640, May 2004.

S. McCracken, Z. Zilic and H. Chan, "Real Laboratories in Distance Education", Journal on Computing and Information Technology", Vol. 11, No. 1, pp. 6776, Jun. 2003.

Z. Zilic and Z. G. Vranesic. "A Deterministic Multivariate Polynomial Interpolation Algorithm for Small Finite Fields", IEEE Transactions on Computers ,Vol. 37, No. 2, pp. 11001105,
Sep. 2002.

M. Boule and Z. Zilic. "An FPGA Move Generator for the Game of Chess", Journal of International Computer Chess Association, ICGA Journal , Vol. 25, No. 2, pp. 8596, Jun. 2002.

Y. Danan and Z. Zilic. "A Highly Adaptive Network Processor for FPGAs", IEEE Computer Architecture Newsletter , pp. 6471, Oct. 2001.

Z. Zilic and Z. G. Vranesic. "Using Decision Diagrams to Design ULMs for
FPGAs", IEEE Transactions on Computers, Vol. 47, No. 9, pp. 971982,
September 1998.

Z. Zilic and Z. G. Vranesic. "Polynomial Interpolation Algorithms for ReedMuller
Transform for Incompletely Specified Functions", Journal of MultipleValued
Logic. Vol. 2, pp. 217243, Aug. 1997.

Z. Zilic and Z. G. Vranesic.
"A
MultipleValued ReedMuller Transform for Incompletely Specified Functions",
IEEE Transactions on Computers, vol. 44, No. 8, pp. 10121020, August
1995.

Z. Zilic, "Experiments with Data Compression Methods in Digital Image Compression",
Automatika,
vol. 31, No. 12, pp. 3136, Jun. 1990.
Conference Papers
 S. Bourduas and Z. Zilic, "A Hybrid Ring/Mesh Interconnect for NetworkonChip Using Hierarchical Rings for Global Routing", Proceedings of IEEE International Symposium on NetworksonChips, NOCS 2007 , May 2007.
 A. Chattopadhyay and Z. Zilic, "Reconfigurable Clock Distribution Circuitry", Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS 2007, May 2007.
 H. Chan and Z. Zilic, "A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits", Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS 2007, May 2007.
 M. Boule, JS. Chenard and Z. Zilic, "Assertion Checkers in Verification, Silicon Debug and InField Diagnosis", Proceedings of International Symposium on Quality Electronic Design, ISQED 2007, Mar. 2007.
 Z. Zilic, K. Radecka and A. Kazamipur, "Reversible Technology Mapping from Nonreversible Specifications", Proceedings of ACM/IEEE Design Automation and Test in Europe, DATE'07, April. 2007.
 M. Boule and Z. Zilic, "Efficient AutomataBased AssertionChecker Synthesis of SEREs for Hardware Emulation", Proceedings of the 12th ACM/IEEE Asia and South Pacific Design Automation Conference, ASPDAC2007, Jan. 2007.
 Y. Pang, K. Radecka and Z. Zilic, "Algorithms for Compositions of Arithmetic Transforms and Their Extensions", Proceedings of IEEE International Conference on Electronics, Circuits and Systems, ICECS06, Dec. 2006.
 Y. Pang, K. Radecka and Z. Zilic, "Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion", Proceedings of IEEE International Conference on Electronics, Circuits and Systems, ICECS06, Dec. 2006.
 M. Boule and Z. Zilic, Efficient AutomataBased AssertionChecker Synthesis of PSL Properties, Proceedings of IEEE International High Level Design Validation and Test Workshop, HLDVT 2006 , Nov. 2006.
 S. Bourduas, JS. Chenard and Z. Zilic, "A RTLLevel Analysis of a Hierarchical Ring Interconnect for NetworkonChip MultiProcessors", Proceedings of International SystemonaChip Design Conference, ISOCC 2006 , Oct. 2006.
 Y. Fan, Y. Cai, L. Fang, A. Verma, W. Burchanowski, Z. Zilic and S. Kumar, "An Accelerated Jitter Tolerance Test Technique on ATE for 1.5 Gb/S and 3 GB/s SerialATA", Proceedings of IEEE International Test Conference, ITC 06, Oct. 2006.
 M. Boule, JS. Chenard and Z. Zilic, "Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug", Proceedings of IEEE International Conference on Computer Design, ICCD 06, Oct. 2006.
 A. Chattopadhyay and Z. Zilic, "ReferenceBased Clock Distribution Architectures", Proceedings of IEEE International Midwest Symposium on Circuits and Systems, Aug. 2006.
 R. Zhang, Z. Zilic and K. Radecka, "Structuring Measurements for Modeling and the Deployment of Industrial Wireless Networks", Proceedings of IEEE International Symposium on Industrial Electronics, ISIE '06, Jul. 2006.
 M. Prokic, JS. Chenard, R. Zhang and Z. Zilic, "LowPower Personal Area Network Application Development Platform", Proceedings of IEEE International Symposium on Industrial Electronics, ISIE '06, Jul. 2006.
 S. Bourduas, B. Kuo, Z. Zilic and N. Manjikian, "Modeling and Evaluation of an EnergyEfficient Hierarchical Ring Interconnect for SystemonChip Multiprocessors", Proceedings of IEEENEWCAS Conference, Jun. 2006.
 A. Chureau, JF. Boland, Y. Savaria, C. Thibeault and Z. Zilic, "Building Heterogeneous Functional Prototypes Using Articulated Interfaces", Proceedings of IEEENEWCAS Conference, Jun. 2006.
 R. Zhang, Z. Zilic and K. Radecka, "EnergyEfficient SoftwareBased SelfTest of Wireless Sensor Network Nodes", Proceedings of IEEE VLSI Test Symposium, VTS '06, Apr. 2006.
 M. Boule and Z. Zilic, "Incorporating Efficient Assertion Checkers into Hardware Emulation and Simulation", Proceedings of IEEE International Conference on Computer Design, ICCD 05, Oct. 2005.
 M. Prokic, JS. Chenard, A. U. Khalid, R. Zhang and Z. Zilic, "IEEE 802.15.4 Wireless Conference Management System, Proceedings of IEEE International Midwest Symposium on Circuits and Systems, Aug. 2005.
 JS. Chenard, C. Y. Chiu, Z. Zilic and M. Popovic, "Design Methodology for Wireless Nodes with Printed Antenna", Proceedings of ACM/IEEE Design Automation Conference, DAC 05, Jun. 2005.
 JS. Chenard, A. U. Khalid, M. Prokic, R. Zhang, KL. Lim, A. Chattopadhyay and Z. Zilic, "Expandable and Robust Laboratory for Microprocessor Systems", Proceedings of IEEE International Conference on Microelectronic Systems Education, MSE05, Jun. 2005. Honorary Mention
 H. Chan and Z. Zilic, "Modeling Layout Effects for Sensitivitybased Analog Circuits Optimization", Proceedings of International Symposium on Quality Electronic Design, ISQED 05 , Mar. 2005.
 JF. Boland, C. Thibeault and Z. Zilic, "Using Matlab and Simulink in a SystemC Verification Environment", Proceedings of Design and Verification Conference, DVCon, Feb. 2005. Best Paper Award
 M. W. Chiang, Z. Zilic, JS. Chenard and K. Radecka, "Architectures of Increased Availability Wireless Sensor Network Nodes", IEEE International Test Conference, ITC, Oct. 2004.
 A. U. Khalid, Z. Zilic and K. Radecka, "FPGA Emulation of Quantum Circuits", IEEE International Conference on Computer Design , Oct. 2004.

JF. Boland, C. Thibeault and Z. Zilic, "Efficient MultiAbstraction Level Functional Verification Methodology for DSP Applications", Global Signal Processing Expo and Conference, GSPx, Oct. 2004.
 K. L. Lim and Z. Zilic, "A Novel Phase Detector for PAM4 Clock Recovery in High Speed Serial Links", IEEE International System on Chip Conference Sep. 2004.
 Y. Fan and Z. Zilic, "A Novel Scheme of Implementing High Speed AWGN Communication Channel Emulators in FPGAs", IEEE International Symposium on Circuits and Systems, May 2004.

S. McCracken and Z. Zilic, "Design for Testability of FPGA Blocks", Proceedings of IEEE International Symposium on Quality Electronic Design, Mar. 2004.
 Y. Fan, Z. Zilic and MW. Chiang, "A Versatile High Speed Bit Error Rate Testing Scheme", Proceedings of IEEE International Symposium on Quality Electronic Design, Mar. 2004.

H. Chan and Z. Zilic, "Estimating PhaseLocked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach", Proceedings of IEEE International Symposium on Quality Electronic Design, Mar. 2004.
 MW. Chiang and Z. Zilic, "Layered Approach to Designing Test System Interfaces, Proceedings of IEEE VLSI Test Symposium, Apr. 2003.
 A. Chattopadhyay and Z. Zilic, "A Globally Asynchronous Locally Dynamic System for ASICs and SoCs", Proceedings of ACM Great Lakes Symposium on VLSI, Apr. 2003.
 K. Radecka and Z. Zilic, "On Combinational Verification by Universal Test Set Simulation, SAT and BDDs", Proceedings of 6th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr. 2003.
 Y. Fan and Z. Zilic, "Testing for Bit Error Rates in FPGAs", Proceedings of ACM International Symposium on Field Programmable Gate Arrays , Feb. 2003.
 K. Radecka and Z. Zilic, "Specifying and Verifying Imprecise Sequential Datapaths by Arithmetic Transforms", Digest of Technical Papers, IEEE/ACM International Conference on ComputerAided Design , Nov. 2002.
 W. Zhu, Z. Zilic and R. Negulescu, "A Singlerail Handshake CDMA Correlator", Proceedings of IEEE International Conference on Electronic Circuits and Systems , Sep. 2002.
 A. Chattopadhyay and Z. Zilic, "High Speed Asynchronous Structures for Interclock Domain Communication", Proceedings of IEEE International Conference on Electronic Circuits and Systems , Sep. 2002.
 C. Cote and Z. Zilic, "Automated SystemC to VHDL Translation in Hardware/Software Codesign", Proceedings of IEEE International Conference on Electronic Circuits and Systems , Sep. 2002.
 H. H. Y. Chan and Z. Zilic, "Substrate Coupling Fault Testing in SystemonaChip Digital Circuits", invited presentation at Proceedings of IEEE International Midwest Symposium on Circuits and Systems, Tulsa, Aug. 2002.
 J. Radecki, Z. Zilic and K. Radecka, "Echo Cancellation in IP Networks", invited presentation at Proceedings of IEEE International Midwest Symposium on Circuits and Systems, Tulsa, Aug. 2002.
 M. Boule and Z. Zilic, "FPGA Move Generator for the Game of Chess", Proceedings of IEEE Custom Integrated Circuits Conference, May 2002.
 Z. Zilic and K. Radecka, "On Role of Superfast Transforms in Speeding up Quantum Algorithms", Proceedings of IEEE International Symposium on Multiple Valued Logic, May 2002.
 B. Polianskikh and Z. Zilic, "Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection", Proceedings of IEEE International Symposium on Multiple Valued Logic, May 2002.
 S. McCracken and Z. Zilic, "FPGA Test Time Reduction Through a Novel Interconnect Testing Scheme", Proceedings of ACM International Symposium on Field Programmable Gate Arrays , Feb. 2002.

K. Radecka and Z. Zilic, "Identifying Redundant Wires for Synthesis and Verification", Proceedings of IEEE Asian Design Automation Conference, ASPDAC , Bangalore, Jan. 2002.

K. Radecka and Z. Zilic, "Identifying Redundant Gate Replacements in Verification
by Error Modeling", Proceedings of IEEE International Test Conference, Oct. 2001.

K. Radecka and Z. Zilic, "Arithmetic Transforms for Verification of Sequential
Datapaths", Proceedings of IEEE International Conference on Computer Design, Sept. 2001.

I. Brynjolfson and Z. Zilic, "Clock Managed System on a Chip", Proc.
IEEE ASIC/SOC Conference, Sept. 2001.

B. Polianskikh and Z. Zilic, "New Embedded Memory for Enhanced Yield, Performance
and Power Consumption", Proc. IEEE International Conference on Electronic
Circuits and Systems, Aug. 2001.

H. Chan and Z. Zilic, "A Practical Substrate Modeling Algorithm with Active
Guardband Macromodel for MixedSignal Substrate Coupling Verification",
Proc. IEEE International Conference on Electronic Circuits and Systems,
Aug. 2001.

K. Radecka, Z. Zilic and K. Khordoc, "Combinational Verification by Simulation,
SAT and BDDs", Proc. IEEE International Conference on Electronic Circuits
and Systems, Aug. 2001.

B. Polianskikh and Z. Zilic, "Induced ErrorCorrecting Code for 2bitpercell
MultiLevel DRAM", Proc. IEEE Midwest Symposium on Circuits and Systems,
Aug. 2001.

H. Chan and Z. Zilic, "Substrate Coupled Noise Reduction and Active Noise
Suppression Circuits for MixedSignal on a Chip Designs", Proc. IEEE International
Midwest Symposium on Circuits and Systems, Aug. 2001. IEEE Myril B. Reed Best Paper Award

K. Radecka and Z. Zilic, "Relating Arithmetic and Walsh Spectra for Verification
by Error Modeling", Proc. 5th International Workshop on Applications
of ReedMuller Expansions in Circuit Design, Aug. 2001.

K. Radecka, Z. Zilic and K. Khordoc, "Arithmetic Transform in Verification
of Sequential Datapaths", Pres. Ph. D. Forum at Design Automation Conference,
Jun. 2001.

Z. Zilic, "Phase and DelayLocked Loops Clock Control in Digital Systems",
Online Symposium of Electrical Engineering, Boston, Massachussets,
Jul. 2001.

W. Zhu, R. Negulescu and Z. Zilic, "Using Design Patterns for Fast Hardware/Software
Performance Estimation", Proc. IEEE International Conference on Telecommunications
, Bucharest, Romania, Jun. 2001.

I. Brynjolfson and Z. Zilic, "A New PLL Design for Clock Management Applications",
Proc. Int. Symposium on Circuits and Systems , Sydney, Australia,
May 2001.

R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa,
A. Grbic, M. Gusat, R. Ho, G. Lemieux. K. Loveless, N. Manjikian,
P. McHardy, S. Srbljic, M. Stumm Z. Vranesic and Z. Zilic, "The NUMAchine
Multiprocessor", Proc. Int. Conf. Parallel Processing, ICPP2000,
Toronto, ON, Aug. 2000.

S. McCracken, Z. Zilic and H. Chan, "Real Laboratories in Distance
Education", Proc. Int. Conf. Adv. Infrastructure for Business, Science
and Education on Internet, SSGRR2000, L'Aquilla, Italy, Aug.
2000.

I. Brynjolfson and Z. Zilic , "LowPower Clock Management for FPGAs", Proc.
Custom Integrated Circuits Conference, CICC 2000, Orlando,
FL, May. 2000.

K. Radecka and Z. Zilic, "Using Arithmetic Transform for Verification of
Datapath Circuits via Error Modeling", Proc. VLSI Test Symposium, VTS
2000, Montreal, QC, May 2000.

I. Brynjolfson and Z. Zilic , "FPGA Clock Management for LowPower Applications",
Proc.
Int. Symposium on FPGAs, FPGA 2000, Monterrey, CA, Feb.
2000., poster.

Z. Zilic , "Alternatives in Teaching SystemBuilding Skills",
Proc.
Int. Symposium on Microelectronics Systems Education, MSE99, Arlington,
VA, Aug. 1999.

Z. Zilic and K. Radecka, "On Feasible Multivariate Polynomial Interpolations
over Arbitrary Fields", Proc. International Symposium on Symbolic and
Algebraic Computing, Vancouver, BC, Jul. 1999.

A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless,
N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic and Z. Zilic, "Design
and Implementation of the NUMAchine Multiprocessor,"
Proc. 35th IEEE
Design Automation Conference, DAC98, San Francisco, Jun. 1998.

Z. Zilic, Z. G. Vranesic and K. Radecka, "A Finite Field Polynomial Interpolation
Algorithm", Ninth International Approximation Theory Conference, AT
IX, Nashville, Tennessee, Jan. 1998.

Z. Zilic, Z. G. Vranesic and K. Radecka, "A Small Finite Field Polynomial
Interpolation Algorithm", Fourth International Conference on Finite
Fields and Applications, Fq4, Waterloo, Ontario, Aug. 1997.

S. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley,
M. Gusat, K. Loveless, Z. Zilic and S. Srbljic "Experience in Designing
a LargeScale Multiprocessor using FieldProgrammable Devices and Advanced
CAD Tools, in Proc. 33rd Design Automation Conference, DAC96, Las
Vegas, Jun. 1996.

Z. Zilic and Z. G. Vranesic, "Parallel Sparse Finite Field Polynomial Interpolation"
Proc.
Workshop on Randomized Parallel Computing, pp. 2125, Honolulu, Apr.
1996.

Z. Zilic and Z. G. Vranesic, "New
Interpolation Algorithms for ReedMuller Forms" , 26th International
Symposium on MultipleValued Logic, Santiago De Campostela, Spain, May
1996.

Z. Zilic and Z. G. Vranesic, Using
BDDs to Design ULMs for FPGAs, Proceedings of the Fourth International
Symposium on FPGAs, Monterey, February 1996. pp. 2430. color
slides

Z. Zilic and Z. G. Vranesic, "ReedMuller
Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation",
Proceedings
of the 25th International Symposium on MultipleValued Logic, Bloomington,
Indiana, May 1995.

T. Abdelrahman, S. Brown, T. Mowry, K. Sevcik, M. Stumm, Z. Vranesic, S.
Zhou, A. Elkateeb, M. Gusat, P. Pereira, B. Gamsa, R. Grindley, O. Krieger,
G. Lemieux, K. Loveless, N. Manjikian, G. Ravindran, S. Srbljic and Z.
Zilic , "An Overview of the NUMAchime Multiprocessor Project", Supercomputing
Symposium SS'94, pp. 283295, Toronto, Jun. 1994.

Z. Zilic and Z. G. Vranesic,
"Multiple Valued Logic in FPGAs", Proceedings of 36th Midwest Symposium
on Circuits and Systems, pp. 15531556, Detroit, Michigan, August 1993.

Z. Zilic and Z. G. Vranesic,
"CurrentMode CMOS Galois Field Circuits", Proceedings of the 23rd
International Symposium on MultipleValued Logic", pp. 245250, Sacramento,
California, May 1993.

Z. Zilic and G. Peskir, "Performance Issues in IEEE 802.6 MAN Subnetwork",
Proceedings of the Mediterranean IEEE Conference "Melecon '91", pp. 10111014,
Ljubljana, Slovenia, May 1991.

V. Glavinic and Z. Zilic, "An Integrated Environment for Specification
of OSI Systems", Proceedings of the Mediterranean IEEE Conference "Melecon
'91", pp. 10071010, Ljubljana, Slovenia, May 1991.

D. Bosnar and Z. Zilic, "Using Formalisms for Concurrent Process Description
in Functional Description of Digital Systems", Conference Etan '91, Ohrid,
Macedonia, May 1991.

Z. Zilic, "Data Compression Methods in Digital Image Compression", Conference
YUGRAPH '90, Dubrovnik, Croatia, May 1990.

Z. Zilic, "Model of One CSMA/CDBased Access Method", Proceedings of the
Conference Etan '90, pp. 243350, Zagreb, Croatia, May 1990. Honorary Mention.
Patents
and Inventions