Simple MOSFET Bias Network (No Feedback Mechanism)

** Circuit Description **
* dc supply
Vdd 1 0 DC +15V
* amplifier circuit
M1 3 4 0 0 nmos L=100u W=100u
Rg1 1 4 1.5Meg
Rg2 4 0 500k
Rd 1 2 2k
* drain current monitor 
Vdrain 2 3 0
* mosfet model statement (by default, level 1)
.model nmos nmos (kp=2m Vto=+2V lambda=0)
** Analysis Requests **
.OP
.SENS I(Vdrain)
** Output Requests **
.end