A Cascade Of Enhancement-Load Inverters (dynamic effects included)

** Circuit Description **
* dc supplies
Vdd 1 0 DC +5V
* input digital signal
Vi 3 0 PWL (0,0V 10ns,0V 10.1ns,5V 110ns,5V 110.1ns,0V 210ns,0V)
* 1st MOSFET inverter circuit
M1 2 3 0 0 MN L=3um W=9um
M2 1 1 2 0 MN L=9um W=3um
Cl1 2 0 0.1pF
* 2nd MOSFET inverter circuit
M3 4 2 0 0 MN L=3um W=9um
M4 1 1 4 0 MN L=9um W=3um
Cl2 4 0 0.1pF
* BNR 3um transistor model statements (level 3)
.MODEL MN nmos (level=3 vto=.7 kp=4.e-05 gamma=1.1 phi=.6 
+ lambda=.01 rd=40 rs=40  pb=.7 cgso=3.e-10 cgdo=3.e-10
+ cgbo=5.e-10 rsh=25 cj=.00044  mj=.5 cjsw=4.e-10 mjsw=.3
+ js=1.e-05 tox=5.e-08 nsub=1.7e+16  nss=0 nfs=0 tpg=1 xj=6.e-07
+ ld=3.5e-07 uo=775  vmax=100000  theta=.11  eta=.05 kappa=1)
** Analysis Requests **
.TRAN 0.5ns 210ns 0ns 0.5ns
** Output Requests **
.Plot TRAN V(2) V(3) V(4)
.probe
.end