A DCFL GaAs Gate

** Circuit Description **
* dc supplies
Vdd 1 0 DC +1.5V
* input signal
Vi 3 0 PWL (0,0V 1ns,0V 1.1ns,700mV 3ns,700mV 3.1ns,0V 5ns,0V)
* amplifier circuit
B1 2 3 0 enchancement_n_mesfet 50
B2 1 2 2 depletion_n_mesfet 6
Cp1 2 0 30fF
B3 4 2 0 enchancement_n_mesfet 50
B4 1 4 4 depletion_n_mesfet 6
* mesfet model statements (by default, level 1)
.model enchancement_n_mesfet gasfet (beta=0.1m Vto=+0.2V lambda=0.1 
+                    n=1.1 Is=5e-16 Cgd=1.2e-15 Cgs=1.2e-15 Rs=2500)
.model depletion_n_mesfet gasfet (beta=0.1m Vto=-1.0V lambda=0.1
+                    n=1.1 Is=5e-16 Cgd=1.2e-15 Cgs=1.2e-15 Rs=2500)
** Analysis Requests **
.DC Vi 0V 0.8V 10mV
.TRAN 0.1ns 5ns 0s 0.1ns
** Output Requests **
.PLOT DC V(2)
.PLOT TRAN V(2)
.probe
.end